Description

This pull request fixes misclassification of certain .v Verilog files that were previously identified as Rocq Prover or Coq due to syntax edge cases. These cases include:

• Module stubs where the module keyword is followed directly by the port list with no space (e.g., module foo(...))
• Files consisting mainly of `pragma protect directives (common in encrypted IP cores)
• Compact syntax using always@ or initial@ without space before the sensitivity list

The updated heuristics.yml pattern broadens the existing Verilog match to allow for:

• Optional spacing before # and ( in module declarations
• `pragma as a valid Verilog preprocessor directive
• Optional spacing before @ in always and initial blocks

Two new .v samples are added to demonstrate these cases, and an existing sample (button_debounce.v) is updated to include a real-world use of always@.

Checklist:

• I am fixing a misclassified language
  • I have included a new sample for the misclassified language:
    • Sample source(s):
      • module_stub.v: Vivado-generated module stub
      • encrypted_module.v: encrypted IP file
    • Sample license(s):
      • Vivado-generated code: compatible with example/sample use under Xilinx’s tools
    • Updated source(s):
      • button_debounce.v: Change always @ ( to always@( to provide an example of the possibility of no whitespace between these operators.
  • I have included a change to the heuristics to distinguish my language from others using the same extension.

Supporting Evidence

• GitHub code search shows both always @ and always@ are widely used:
  • always @: ~618,000 results
  • always@: ~60,900 results
• Example of real-world use of always@:
  1bitSDR/NCO.v#L36